As the critical dimensions of integrated circuits continue to shrink, the fabrication of gate electrodes for complementary metal-oxide-semiconductor (CMOS) transistors has advanced to replace silicon dioxide gate dielectrics and polysilicon gate electrodes with high-k dielectric material and electrically conductive materials such as metals, respectively. A replacement metal gate (RMG) process is often used to form the gate electrode. An exemplary replacement metal gate process includes forming a sacrificial gate oxide and a sacrificial polysilicon gate between a pair of spacers on a semiconductor substrate. After further processing steps, such as an annealing process, the sacrificial gate oxide and sacrificial polysilicon gate are removed and the resulting trench is filled with a high-k dielectric and one or more replacement metal layers. The replacement metal layers can include work function materials as well as a metallic gate electrode, which may include aluminum (Al), tungsten (W), and/or other metals.
Processes such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), electroplating (EP), and electroless plating (ELP) may be used to form the one or more replacement metal gate layers that form the replacement metal gate stack. Unfortunately, as critical dimensions decrease, issues such as trench overhang and void formation become more prevalent and pose a greater challenge to overcome. This is due to the smaller gate dimensions. Specifically, at smaller dimensions, the aspect ratio of the trench used to form the replacement metal gate electrode becomes higher as the replacement metal layers form on the trench sidewalls. Metallization of high aspect ratio trenches quite often results in void formation.
Additional issues arise with lateral scaling. For example, lateral scaling presents issues for the formation of contacts. When the contacted gate pitch is reduced to about 64 nanometers (nm), it is difficult to form contacts between the gate lines while maintaining reliable electrical isolation properties between the gate line and the contact. Self-aligned contact (SAC) methodology has been developed to address this problem. Conventional SAC approaches involve recessing the replacement metal gate stack, which includes recessing both work function metal liners and a gate electrode. Work function metal lines may include titanium nitride (TiN), titanium silicon nitride (TiSixNy), tantalum nitride (TaN), titanium carbide (TiC), tantalum carbide (TaC), and/or titanium aluminum nitride (TiAlN), and gate electrode materials may include aluminum (Al), tungsten (W), cobalt (Co), copper (Cu) or the like. A dielectric cap may be formed overlying the replacement metal gate stack followed by chemical mechanical planarization (CMP). To set the correct work function for the device, work function layers with varied thicknesses ranging from about 1 to 7 nanometers (nm) are typically used. The work function layers may include a variety of materials, as mentioned above, with a total thickness of more than 5 nm. As gate length continues to scale down, for example for sub-15 nm gates, the replacement metal gate electrode structure is so narrow that it may be “pinched-off” by the work function layers, leaving little or no space remaining for the lower-resistance metallic gate electrode. The reduced space for the gate electrode increases the overall electrical resistance of the replacement metal gate stack. This often results in high resistance issues for devices with small gate lengths, and also causes problems in the SAC replacement metal gate recess process.
Conventional replacement metal gate stacks may suffer from significant threshold voltage variations due in part to variation in the thicknesses of the work function layers. Further, the diffusion of aluminum, oxygen, or fluorine (where fluorine is often used in tungsten deposition processes) into the work function layers and into the high-k gate dielectric can alter the threshold voltage of the replacement metal gate stacks. Conventional processing of titanium nitride and subsequent plasma treatment that can also cause threshold voltage variations of the replacement metal gate stacks. In addition, conventional replacement metal gate for CMOS processes may include the deposition of one work function layer(s) that are appropriate for a p-type field effect transistor (“pFET”) and one or more work function layer(s) that are appropriate for an n-type field effect transistor (“nFET”), and this process may involve the removal of the work function layer that is appropriate for one type of FET to prepare for deposition of the work function layer that is appropriate for the other type of FET. The removal steps often cause non-uniformity issues and surface modification in the FET region, which can also result in threshold voltage variation of the replacement metal gate stacks.
Accordingly, it is desirable to provide improved integrated circuits having replacement metal gate stacks and methods for fabricating such improved integrated circuits, particularly as aspect ratios of the replacement metal gate electrodes continue to scale down. Also, it is desirable to provide integrated circuits with replacement metal gate stacks that exhibit low gate electrode resistance and methods for fabricating such integrated circuits. Further, it is desirable to provide integrated circuits with replacement metal gate stacks that exhibit reduced threshold voltage variation and methods for fabricating such integrated circuits. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.